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Book Title: Logic Synthesis and Verification
Publication Date: 2001-11-30
Pages: 454
Number of Pages: Xv, 454 Pages
Language: English
Publication Name: Logic Synthesis and Verification
Publisher: Springer
Publication Year: 2001
Subject: Electronics / Circuits / Logic, Computer Science, Cad-Cam, Electronics / Circuits / General, Logic Design
Type: Textbook
Item Weight: 64.9 Oz
Item Length: 9.3 in
Author: Tsutomu Sasao
Subject Area: Computers, Technology & Engineering
Item Width: 6.1 in
Series: The Springer International Series in Engineering and Computer Science Ser.
Format: Hardcover
